Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected to a word-select line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a column bit line.
The memory array is accessed by a row decoder activating a row of memory cells by selecting the word-select line connected to a control gate of a memory cell. In addition, the word-select lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
The floating-gate memory cells and the select lines are normally formed concurrently and include a first dielectric layer, e.g., an oxide, disposed on a substrate, such as silicon. A first conductive (or polysilicon) layer overlies the first dielectric layer, and a second dielectric layer, such as an oxide-nitride-oxide (ONO) layer, overlies the first conductive layer. A second conductive (or polysilicon) layer is disposed on the second dielectric layer, and a third conductive layer, such as a metal or polycide layer, is disposed on the second conductive layer and is in electrical contact therewith. A protective cap layer typically overlies the third conductive layer, and a bulk insulation layer (or dielectric layer) overlies the protective cap layer. The first dielectric layer acts as a tunnel dielectric layer for the floating-gate memory cells and a gate dielectric layer for the select line.
The first polysilicon layer of the memory cells forms a floating gate, while the second polysilicon layer and the metal or polycide layer form a control gate (or word line) that spans the entire array, e.g., all of the columns of memory cells (or NAND strings). The first and second polysilicon layers of the select lines are interconnected, or shorted together, to form a control gate that includes the first and second polysilicon layers and the metal or polycide layer and that that spans the entire array, e.g., all of the columns of the array.
Currently, the first and second polysilicon layers of the select lines are shorted at one location for a number of select gates. This is usually accomplished by forming a metal or polycide strap on the bulk insulation layer. A first contact is passed through the bulk insulation layer and the protective cap layer and contacts the metal or polycide layer, which is in electrical contact with the second polysilicon layer. An extension of the first polysilicon layer extends beyond the second dielectric layer, the second polysilicon layer, the metal or polycide layer, and the protective cap layer, and the bulk insulation layer is disposed on the extension of the first polysilicon layer. A second contact is passed through the bulk insulation layer and is connected between the strap and the extension of the first polysilicon layer so that the strap shorts the first and second polysilicon layers together. However, this requires extra processing steps, e.g., at least one additional etch. Moreover, for large memory arrays having a large number of columns, shorting the first and second polysilicon layers at one location results in select lines with relatively high resistance because the select lines are primarily of polysilicon. The relatively high resistance acts to slow down the operation of the select gates along the select line.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative select lines for NAND memory devices.